`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2017/11/07 10:58:03
// Design Name: 
// Module Name: mips
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module mips(
	input wire clk,rst,
	output wire[31:0] pcF,
	input wire[31:0] instrF,
	output wire memwriteM,
	output wire[31:0] aluoutM,writedataM,
	input wire[31:0] readdataM,
	output wire[3:0] datawenM
    );
	
	wire [5:0] opD,functD;
	wire [4:0] rtD;
	wire regdstE,alusrcE,
			pcsrcD,branchD,jumpD,jalD,jrD,balD,
			jalE,balE,
			memtoregE,memtoregM,memtoregW,
			regwriteE,regwriteM,regwriteW;
	wire [4:0] alucontrolE;
	wire stallE,flushE,equalD;
	wire [1:0] hi_mdrE,lo_mdrE;

	wire [1:0] memsizeM;
	wire memsigndM;

	wire [1:0] memsizeW;
	wire memsigndW;


	controller c(
		clk,rst,
		//decode stage
		opD,functD,rtD,
		pcsrcD,branchD,equalD,jumpD,jalD,jrD,balD,
		mfhiD, mfloD,//yyx
		hi_writeD,lo_writeD,//yyx
		//execute stage

		memtoregE,alusrcE,
		regdstE,regwriteE,	
		alucontrolE,
		jalE,balE,
		mfhiE,mfloE,//yyx
		hi_writeE,lo_writeE,//yyx
		hi_mdrE,lo_mdrE,
		//mem stage
		memtoregM,memwriteM,
		regwriteM,
		memsizeM,memsigndM,
		hi_writeM, lo_writeM,//yyx
		//write back stage
		memtoregW,regwriteW,
		memsizeW,
		memsigndW,
		hi_writeW, lo_writeW,//yyx

		stallE,//yyx
    	flushE//yyx
		);
	datapath dp(
		clk,rst,
		//fetch stage
		pcF,
		instrF,
		//decode stage
		pcsrcD,branchD,
		jumpD,jalD,jrD,balD,
		equalD,
		opD,functD,rtD,
		//execute stage
		memtoregE,
		alusrcE,regdstE,
		regwriteE,
		alucontrolE,
		mfhiE,mfloE,//yyx
		hi_mdrE,lo_mdrE,
		//flushE,
		jalE,balE,
		//mem stage
		memtoregM,
		regwriteM,
		aluoutM,writedataM,
		readdataM,
		memsizeM,memsigndM,
		memwriteM,
		hi_writeM,lo_writeM, //yyx
		//writeback stage
		memtoregW,
		regwriteW,
		memsizeW,
		memsigndW,
		hi_writeW,lo_writeW, //yyx

		datawenM,
		
		stallE,//yyx
    	flushE//yyx
	    );
	
endmodule
